The present invention relates to a wiring technique, and, more specifically, to a technique that can be effectively utilized for forming a wiring layer to supply an operation voltage to the electronic circuitry in a semiconductor integrated circuit device.
A semiconductor integrated circuit is formed by a combination of many electronic circuits each of which is supplied with an operation voltage (or often referred to as power source voltage) through a wiring layer (or often referred to as power source wiring).
The area of a semiconductor substrate in which a semiconductor integrated circuit is formed, is ever increasing accompanying the trend toward constructing semiconductor integrated circuits having larger scales and larger capacities. Therefore, the length of the wiring layer for supplying the operation voltage is inevitably increased, resulting in an increase in the parasitic impedance which is the sum of the parasitic inductive and the parasitic resistance.
Study has also been vigorously directed toward increasing the operation speed of the semiconductor integrated circuit devices, and a technique has been developed to charge and discharge, at high speeds, the capacitive load of a signal propagation path in the semiconductor integrated circuit. When the electronic circuit is operated, therefore, a large current flows into the wiring layer which has a large parasitic impedance, and the operation voltage applied to the wiring layer undergoes variation due to the parasitic impedance. Variation in the operation potential causes other electronic circuits to operate erroneously. For example, if amongst the other electronic circuits there is included a complementary (MOS(C-MOS) inverter circuit that properly operates an operation voltages of 5 volts and zero volt, the following error develops in the operation.
If now the operation voltage of 5 volts drops down to 4.2 volts due to the parasitic impedance in the wiring layer, a logic input threshold voltage of the CMOS inverter circuit becomes lower than a predetermined value. In the worst case, therefore, an input signal of the low level will be erroneously determined to be an input signal of the high level. If a zero-volt operation voltage changes to 0.8 volts due to the parasitic impedance in the wiring layer, the logic input threshold voltage of the CMOS inverter circuit becomes greater than a predetermined value, and an input signal of the high level will be erroneously determined to be an input signal of the low level.